HEAT TRANSFER IN NANOSTRUCTURES
When nanoscale features, such as thin films or extremely localized heating regions are present in devices, heat transfer becomes partially ballistic. Such non-continuum effects to heat transfer is defined by the mean free path of the energy carriers. The heat carrying capacities and the mean free paths of energy carriers within a material vary significantly. Thus, it is important to know the mean free path - thermal conductivity relationship of all energy carriers inside a material to understand the impact of nanoscale effects to heat transfer. This relationship, that is still missing for many.
MULTISCALE THERMAL MODELING OF HOTSPOTS
Localized heat generation is a known problem of many semiconductor devices, such as AlGaN/GaN and AlN/β-Ga2o3 High Electron Mobility Transistors (HEMTs). Hotspots formed as a result of localized heat generation in these devices is one of the contributing factors to device reliability. Current heat transport models using finite element modeling techniques ignore the ballistic phonon effects, therefore underestimate the actual hotspot temperatures. Thus, multiscale tool that will simulate the entire device with reasonable computational cost are required.
ELECTRO-THERMAL MODELING OF SEMICONDUCTOR DEVICES
Realistic thermal modeling of electronic devices is possible with the knowledge of Joule heating distribution in them. To obtain this information electrical device simulations should be performed. We perform electrical device simulations using SENTAURUS SYNOPSYS TCAD and use this information in accurate thermal models of devices and their packages.
CHIP TO PACKAGE LEVEL THERMAL MANAGEMENT
With the increasing demand of industry, thermal management of electronic devices such as transistors and LEDs become more important. Thermal management solutions should be suggested with proper analysis of not only the package but also the details of the chip structure. In our group the effects of thermal optimization studies on the maximum temperatures inside the devices are investigated by taking temperature dependent thermal conductivities of chip layers, chip geometry and heating distribution into account.
